1. Field of the Invention
The present invention relates to a semiconductor storage device, and particularly, to a semiconductor storage device with a pseudo-pass function.
2. Description of the Related Art
In NAND-type flash memories of semiconductor storage devices, write speed and erase speed are effectively improved by writing data in one page basis, performing erase operations in plural page basis, and so on. In a write operation in page, write data is first serially input. The write data is then input to a register for one page. After that, a write-pulse application and verify read operations are repeated until the write operations are completed for all data in the page. As such, it is necessary to read data after verify read operations from all registers in the page, which can be time-consuming. In view of the above, Japanese Patent Laid-Open No. 2002-140899 discloses an invention with respect to a method for rapidly detecting not only whether all results of verify read operations are passed, but also the number of fails.
On the other hand, when a NAND-type flash memory of a semiconductor storage device is used, detection and correction of bit errors with ECC (Error Checking and Correcting) is an effective solution to ensure sufficient reliability. For example, a standard system using a multi-value NAND-type flash memory is equipped with ECC that may detect and correct a bit error with four symbols per page.
Meanwhile, recent years have seen significant improvements in integration density and capacity of NAND-type flash memories. However, a phenomenon has been observed in these NAND-type flash memories with such improved integration density and capacity: extemporaneous increase in thresholds in a certain memory cell leads to an incorrect data write or erase operation. Such a phenomenon is referred to as, so-called, “extemporaneous bit flips”.
In multi-value NAND-type flash memories, it is believed to be more advantageous, from the viewpoint of cost, to ensure reliability with “extemporaneous bit flips” accepted to some extent. Based on this idea, a “pseudo-pass function” has been developed. The “pseudo-pass function” is a technique that returns “PASS” as a status even if a bit error occurs in one or more bits at the time of completion of a write or erase sequence within a chip. With this technique, if any bit error occurs at the time of completion of a write or erase sequence within the chip, the ECC is performed in a system or flash controller when reading. Therefore, those bit errors pose no problem that include a correctable number of error bits. However, the NAND-type flash memory with the “pseudo-pass function” has a problem that could reduce write or erase speed, possibly leading to degradation in performance of electronics systems using such NAND-type flash memories. In view of the above, Japanese Patent Laid-Open No. 2006-134482 discloses an invention that mitigates such performance degradation.
Further, Japanese Patent Laid-Open No. 2004-192789 discloses an invention of a method for writing data in a semiconductor storage device in order of data units referred to as “pages” (generally, 2 KB+redundant column) and physical write data in a memory cell, in order to improve data reliability associated with refinement.